URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Last modification

• Rev 415 2010-11-08 14:53:17 GMT
• Author: julius

• Log message:

  ORPSoC - ML501 update, working again.
  Documentation update including information on ML501 build
  OR1200 updates to do with instruction cache tag signal when
  invalidate instruction used.
  Added ability to define address to pass to SPI flash when
  booting.
  Added SPI sw test for board which allows inspection of
  data in a flash.

Path	Last modification			Log	RSS feed
openrisc/	415	5215d 14h	julius	View Log	RSS feed
branches/	1	5781d 20h	ocadmin	View Log	RSS feed
tags/	388	5252d 14h	jeremybennett	View Log	RSS feed
trunk/	415	5215d 14h	julius	View Log	RSS feed
bootloaders/	406	5221d 08h	julius	View Log	RSS feed
docs/	359	5274d 18h	julius	View Log	RSS feed
gnu-patches/	170	5342d 16h	jeremybennett	View Log	RSS feed
gnu-src/	414	5216d 09h	jeremybennett	View Log	RSS feed
linux/	380	5254d 13h	julius	View Log	RSS feed
or1ksim/	387	5252d 14h	jeremybennett	View Log	RSS feed
or1k_startup/	2	5781d 19h	marcus.erlandsson	View Log	RSS feed
or1200/	401	5222d 15h	julius	View Log	RSS feed
orpsocv2/	415	5215d 14h	julius	View Log	RSS feed
or_debug_proxy/	376	5259d 20h	julius	View Log	RSS feed
rtos/	174	5342d 15h	jeremybennett	View Log	RSS feed
toolchain_install_scripts/	407	5221d 07h	julius	View Log	RSS feed
uClibc/	382	5254d 13h	julius	View Log	RSS feed