URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Last modification

• Rev 415 2010-11-08 14:53:17 GMT
• Author: julius

• Log message:

  ORPSoC - ML501 update, working again.
  Documentation update including information on ML501 build
  OR1200 updates to do with instruction cache tag signal when
  invalidate instruction used.
  Added ability to define address to pass to SPI flash when
  booting.
  Added SPI sw test for board which allows inspection of
  data in a flash.

Path	Last modification			Log	RSS feed
openrisc/	415	4983d 01h	julius	View Log	RSS feed
branches/	1	5549d 07h	ocadmin	View Log	RSS feed
tags/	388	5020d 01h	jeremybennett	View Log	RSS feed
trunk/	415	4983d 01h	julius	View Log	RSS feed
bootloaders/	406	4988d 18h	julius	View Log	RSS feed
docs/	359	5042d 05h	julius	View Log	RSS feed
gnu-patches/	170	5110d 02h	jeremybennett	View Log	RSS feed
gnu-src/	414	4983d 20h	jeremybennett	View Log	RSS feed
linux/	380	5022d 00h	julius	View Log	RSS feed
or1ksim/	387	5020d 01h	jeremybennett	View Log	RSS feed
or1k_startup/	2	5549d 06h	marcus.erlandsson	View Log	RSS feed
or1200/	401	4990d 02h	julius	View Log	RSS feed
orpsocv2/	415	4983d 01h	julius	View Log	RSS feed
or_debug_proxy/	376	5027d 07h	julius	View Log	RSS feed
rtos/	174	5110d 02h	jeremybennett	View Log	RSS feed
toolchain_install_scripts/	407	4988d 18h	julius	View Log	RSS feed
uClibc/	382	5021d 23h	julius	View Log	RSS feed