URL
https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
Subversion Repositories openrisc_2011-10-31
[/] [openrisc/] [trunk/] [gnu-src/] [gdb-7.1/] [sim/] - Rev 244
Go to most recent revision | Changes | View Log | RSS feed
Last modification
- Rev 244 2010-08-20 10:27:26 GMT
- Author: jeremybennett
- Log message:
- Don't try to skip prologue using SAL info (fails with STABS). Fuller check of prologue. Change register names to rnn from gprnn to match assembler. Add debug option to simulator wrapper.
* or32-tdep.c (or32_register_name): Changed to rnn rather than
gprnn to mach the assembler.
(or32_is_arg_reg, or32_is_callee_saved_reg): Added.
(or32_skip_prologue): Don't use skip_prologue_using_sal. Check for
argument as well as callee saved registers in prologue.
(or32_frame_cache):Check for argument as well as callee saved
registers in prologue.
* wrapper.c: OR32_SIM_DEBUG added to control debug messages.
(sim_close, sim_load, sim_create_inferior, sim_fetch_register)
(sim_stop): Debug statement added.
(sim_read, sim_write): Debug statements now controlled by
OR32_SIM_DEBUG.
(sim_store_register, sim_resume): Debug statement added and
existing debug statements now controlled by OR32_SIM_DEBUG.