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https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [ml501/] [backend/] [bin/] - Rev 486
Last modification
- Rev 415 2010-11-08 14:53:17 GMT
- Author: julius
- Log message:
- ORPSoC - ML501 update, working again.
Documentation update including information on ML501 build
OR1200 updates to do with instruction cache tag signal when
invalidate instruction used.
Added ability to define address to pass to SPI flash when
booting.
Added SPI sw test for board which allows inspection of
data in a flash.