URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Last modification

• Rev 411 2010-11-04 13:09:21 GMT
• Author: julius

• Log message:

  Improved ethmac testbench and software.
  
  Renamed some OR1200 library functions to be more generic.
  
  Fixed bug with versatile_mem_ctrl for Actel board.
  
  Added ability to simulate gatelevel modules alongside RTL modules
  in board build.

Path	Last modification			Log	RSS feed
openrisc/	411	5127d 16h	julius	View Log	RSS feed
branches/	1	5689d 20h	ocadmin	View Log	RSS feed
tags/	388	5160d 14h	jeremybennett	View Log	RSS feed
trunk/	411	5127d 16h	julius	View Log	RSS feed
bootloaders/	406	5129d 08h	julius	View Log	RSS feed
docs/	359	5182d 18h	julius	View Log	RSS feed
gnu-patches/	170	5250d 16h	jeremybennett	View Log	RSS feed
gnu-src/	404	5129d 12h	jeremybennett	View Log	RSS feed
linux/	380	5162d 13h	julius	View Log	RSS feed
or1ksim/	387	5160d 14h	jeremybennett	View Log	RSS feed
or1k_startup/	2	5689d 20h	marcus.erlandsson	View Log	RSS feed
or1200/	401	5130d 15h	julius	View Log	RSS feed
orpsocv2/	411	5127d 16h	julius	View Log	RSS feed
bench/	408	5129d 04h	julius	View Log	RSS feed
boards/	411	5127d 16h	julius	View Log	RSS feed
doc/	410	5128d 16h	julius	View Log	RSS feed
rtl/	411	5127d 16h	julius	View Log	RSS feed
sim/	411	5127d 16h	julius	View Log	RSS feed
bin/	411	5127d 16h	julius	View Log	RSS feed
out/	360	5182d 11h	julius	View Log	RSS feed
run/	6	5659d 08h	julius	View Log	RSS feed
sw/	411	5127d 16h	julius	View Log	RSS feed
or_debug_proxy/	376	5167d 20h	julius	View Log	RSS feed
rtos/	174	5250d 15h	jeremybennett	View Log	RSS feed
toolchain_install_scripts/	407	5129d 07h	julius	View Log	RSS feed
uClibc/	382	5162d 13h	julius	View Log	RSS feed