OpenCores
URL https://opencores.org/ocsvn/pit/pit/trunk

Subversion Repositories pit

[/] [pit/] [trunk/] [rtl/] [verilog/] - Rev 17

Rev

Go to most recent revision | Changes | View Log | RSS feed

Last modification

  • Rev 17 2010-01-27 20:08:01 GMT
  • Author: rehayes
  • Log message:
    Change WISHBONE ack signal so no output is generated when wait states are enabled and the bus transaction is terminated in the first cycle.
Path Last modification Log RSS feed
[FOLDER] pit/ 17  5283d 17h rehayes View Log RSS feed
[NODE][FOLDER] branches/ 1  5572d 08h root View Log RSS feed
[NODE][FOLDER] tags/ 1  5572d 08h root View Log RSS feed
[NODE][FOLDER] trunk/ 17  5283d 17h rehayes View Log RSS feed
[NODE][NODE][FOLDER] bench/ 16  5394d 20h rehayes View Log RSS feed
[NODE][NODE][FOLDER] doc/ 13  5521d 22h rehayes View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 17  5283d 17h rehayes View Log RSS feed
[NODE][NODE][NODE][FOLDER] verilog/ 17  5283d 17h rehayes View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] pit_count.v 2  5571d 17h rehayes View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] pit_prescale.v 2  5571d 17h rehayes View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] pit_regs.v 2  5571d 17h rehayes View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] pit_top.v 10  5523d 21h rehayes View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] pit_wb_bus.v 17  5283d 17h rehayes View Log RSS feed
[NODE][NODE][FOLDER] sim/ 5  5571d 16h rehayes View Log RSS feed
[NODE][FOLDER] web_uploads/ 1  5572d 08h root View Log RSS feed

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.