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[/] [spi_master_slave/] - Rev 20

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Last modification

  • Rev 20 2011-08-11 02:31:05 GMT
  • Author: jdoin
  • Log message:
    - removed folder trunk/bench.
    - added ISE13.1 complete project, with synthesis, map, place & route and timing reports. This project generates bitgen file to program a Digilent Atlys board to verify the cores in FPGA hardware, and include a simulation testbench to simulate the cores.
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[FOLDER] spi_master_slave/ 20  4881d 11h jdoin View Log RSS feed
[NODE][FOLDER] branches/ 1  4968d 07h root View Log RSS feed
[NODE][FOLDER] tags/ 1  4968d 07h root View Log RSS feed
[NODE][FOLDER] trunk/ 20  4881d 11h jdoin View Log RSS feed

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