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[/] [spi_master_slave/] [trunk/] - Rev 10
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Last modification
- Rev 10 2011-07-17 05:21:49 GMT
- Author: jdoin
- Log message:
- v1.11.0080: Changed sampling of MISO in spi_master.vhd (removed the input register).
Verified master+slave cores in silicon on a Spartan-6 FPGA at 100MHz, using Xilinx ISE 13.1 and a Digilent Atlys board. Project is included in trunk/syn/spi_master_atlys.xise.