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[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] - Rev 14
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Last modification
- Rev 14 2010-01-18 07:28:13 GMT
- Author: ghutchis
- Log message:
- - Modified large FIFO to remove "full" signal and store only N-1 words
- changed small FIFO to use memory instance instead of registers
- changed sequence generator to enable more complex tests
- changed sd_mirror to use combinatorial assign output