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https://opencores.org/ocsvn/t6507lp/t6507lp/trunk
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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 128
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Last modification
- Rev 128 2009-03-27 14:28:52 GMT
- Author: gabrieloshiro
- Log message:
- $write and $finish primitives were removed from synthesizable blocks. Latches were removed. Top level were fixed (rw_mem and mem_rw should have the same name). All blocks were synthesized.