URL https://opencores.org/ocsvn/test_project/test_project/trunk

Subversion Repositories test_project

[/] [test_project/] [trunk/] [bench/] [verilog/] - Rev 54

Rev 54 2009-05-20 13:38:53 GMT
Author: julius
Log message:
Added verilog UART decoder for event-driven sim tests (icarus, nc) - removed MAC tests from multiplier tests - not returning right results for some reason - should be looked at

Path	Last modification			Log	RSS feed
test_project/	54	5667d 20h	julius	View Log	RSS feed
branches/	10	5717d 01h	unneback	View Log	RSS feed
tags/	4	5739d 00h	root	View Log	RSS feed
trunk/	54	5667d 20h	julius	View Log	RSS feed
backend/	22	5688d 00h	julius	View Log	RSS feed
bench/	54	5667d 20h	julius	View Log	RSS feed
sysc/	52	5668d 10h	julius	View Log	RSS feed
verilog/	54	5667d 20h	julius	View Log	RSS feed
AT26DFxxx.v	33	5684d 10h	julius	View Log	RSS feed
clk_gen.v	22	5688d 00h	julius	View Log	RSS feed
mt48lc16m16a2.v	22	5688d 00h	julius	View Log	RSS feed
or1200_monitor.v	52	5668d 10h	julius	View Log	RSS feed
orpsoc_testbench.v	54	5667d 20h	julius	View Log	RSS feed
orpsoc_testbench_defines.v	54	5667d 20h	julius	View Log	RSS feed
timescale.v	26	5687d 23h	julius	View Log	RSS feed
uart_decoder.v	54	5667d 20h	julius	View Log	RSS feed
rtl/	54	5667d 20h	julius	View Log	RSS feed
sim/	54	5667d 20h	julius	View Log	RSS feed
sw/	54	5667d 20h	julius	View Log	RSS feed
web_uploads/	6	5738d 18h	root	View Log	RSS feed