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[/] [test_project/] [trunk/] [rtl/] [verilog/] - Rev 42

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Last modification

  • Rev 42 2009-05-06 19:45:47 GMT
  • Author: julius
  • Log message:
    Fixed up to allow compilation with verilator. Mostly separation of modules into appropriate file names. However some vector declaration changes in the smii module has definitely broken it.
Path Last modification Log RSS feed
[FOLDER] test_project/ 42  5685d 19h julius View Log RSS feed
[NODE][FOLDER] branches/ 10  5721d 06h unneback View Log RSS feed
[NODE][FOLDER] tags/ 4  5743d 04h root View Log RSS feed
[NODE][FOLDER] trunk/ 42  5685d 19h julius View Log RSS feed
[NODE][NODE][FOLDER] backend/ 22  5692d 05h julius View Log RSS feed
[NODE][NODE][FOLDER] bench/ 40  5685d 22h julius View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 42  5685d 19h julius View Log RSS feed
[NODE][NODE][NODE][FOLDER] verilog/ 42  5685d 19h julius View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] components/ 42  5685d 19h julius View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] dummy_slave.v 17  5693d 04h unneback View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] eth_defines.v 17  5693d 04h unneback View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] intercon.vm 20  5693d 03h unneback View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] or1200_defines.v 33  5688d 14h julius View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] orpsoc_top.v 42  5685d 19h julius View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] uart_defines.v 17  5693d 04h unneback View Log RSS feed
[NODE][NODE][FOLDER] sim/ 42  5685d 19h julius View Log RSS feed
[NODE][NODE][FOLDER] sw/ 33  5688d 14h julius View Log RSS feed
[NODE][FOLDER] web_uploads/ 6  5742d 23h root View Log RSS feed

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