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[/] [test_project/] [trunk/] [rtl/] [verilog/] - Rev 54

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Last modification

  • Rev 54 2009-05-20 13:38:53 GMT
  • Author: julius
  • Log message:
    Added verilog UART decoder for event-driven sim tests (icarus, nc) - removed MAC tests from multiplier tests - not returning right results for some reason - should be looked at
Path Last modification Log RSS feed
[FOLDER] test_project/ 54  5671d 12h julius View Log RSS feed
[NODE][FOLDER] branches/ 10  5720d 17h unneback View Log RSS feed
[NODE][FOLDER] tags/ 4  5742d 16h root View Log RSS feed
[NODE][FOLDER] trunk/ 54  5671d 12h julius View Log RSS feed
[NODE][NODE][FOLDER] backend/ 22  5691d 16h julius View Log RSS feed
[NODE][NODE][FOLDER] bench/ 54  5671d 12h julius View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 54  5671d 12h julius View Log RSS feed
[NODE][NODE][NODE][FOLDER] verilog/ 54  5671d 12h julius View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] components/ 48  5676d 06h julius View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] dummy_slave.v 17  5692d 15h unneback View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] eth_defines.v 17  5692d 15h unneback View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] intercon.vm 20  5692d 14h unneback View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] or1200_defines.v 33  5688d 01h julius View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] orpsoc_top.v 54  5671d 12h julius View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] uart_defines.v 17  5692d 15h unneback View Log RSS feed
[NODE][NODE][FOLDER] sim/ 54  5671d 12h julius View Log RSS feed
[NODE][NODE][FOLDER] sw/ 54  5671d 12h julius View Log RSS feed
[NODE][FOLDER] web_uploads/ 6  5742d 10h root View Log RSS feed

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