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[/] [test_project/] [trunk/] [rtl/] [verilog/] [components/] [or1k_startup/] - Rev 34

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Last modification

  • Rev 34 2009-05-05 12:49:26 GMT
  • Author: julius
  • Log message:
    Fixed up couple of things. Changed way the test name is defined in sim Makefile
Path Last modification Log RSS feed
[FOLDER] test_project/ 34  5683d 12h julius View Log RSS feed
[NODE][FOLDER] branches/ 10  5717d 16h unneback View Log RSS feed
[NODE][FOLDER] tags/ 4  5739d 15h root View Log RSS feed
[NODE][FOLDER] trunk/ 34  5683d 12h julius View Log RSS feed
[NODE][NODE][FOLDER] backend/ 22  5688d 16h julius View Log RSS feed
[NODE][NODE][FOLDER] bench/ 34  5683d 12h julius View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 34  5683d 12h julius View Log RSS feed
[NODE][NODE][NODE][FOLDER] verilog/ 34  5683d 12h julius View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] components/ 34  5683d 12h julius View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FOLDER] debug_if/ 18  5689d 14h unneback View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FOLDER] ethernet/ 18  5689d 14h unneback View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FOLDER] or1k_startup/ 34  5683d 12h julius View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][NODE][FILE] copyright_OR1K_startup.v 19  5689d 14h unneback View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][NODE][FILE] copyright_spi.v 19  5689d 14h unneback View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][NODE][FILE] flash_wb_32x32.v 19  5689d 14h unneback View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][NODE][FILE] Makefile 19  5689d 14h unneback View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][NODE][FILE] OR1K_startup.v 19  5689d 14h unneback View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][NODE][FILE] OR1K_startup_ACTEL.v 19  5689d 14h unneback View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][NODE][FILE] OR1K_startup_ACTEL_IP.v 19  5689d 14h unneback View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][NODE][FILE] OR1K_startup_generic.v 34  5683d 12h julius View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][NODE][FILE] OR1K_startup_module_inst.v 19  5689d 14h unneback View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][NODE][FILE] OR1K_startup_rom.v 19  5689d 14h unneback View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][NODE][FILE] spi_clgen.v 19  5689d 14h unneback View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][NODE][FILE] spi_defines.v 19  5689d 14h unneback View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][NODE][FILE] spi_flash.v 19  5689d 14h unneback View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][NODE][FILE] spi_shift.v 19  5689d 14h unneback View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][NODE][FILE] spi_top.v 22  5688d 16h julius View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][NODE][FILE] timescale.v 19  5689d 14h unneback View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FOLDER] or1k_top/ 18  5689d 14h unneback View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FOLDER] or1200r2/ 22  5688d 16h julius View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FOLDER] smii/ 22  5688d 16h julius View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FOLDER] tap/ 18  5689d 14h unneback View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FOLDER] uart16550/ 33  5685d 01h julius View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FOLDER] wb_sdram_ctrl/ 22  5688d 16h julius View Log RSS feed
[NODE][NODE][FOLDER] sim/ 34  5683d 12h julius View Log RSS feed
[NODE][NODE][FOLDER] sw/ 33  5685d 01h julius View Log RSS feed
[NODE][FOLDER] web_uploads/ 6  5739d 09h root View Log RSS feed

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