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[/] [tinycpu/] [trunk/] [src/] - Rev 28

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  • Rev 28 2012-05-18 05:14:22 GMT
  • Author: earlz
  • Log message:
    Ok now registerfile is correct. Only using rising_edge. Now DataOut is the same as DataIn when WriteEnable is asserted.
    Some of my tests had to be changed because I was expecting the DataOut to be updated 1 clock cycle after the instruction rather than on the same clock cycle.
    Now it's truly single-cycle and without all the weird regIn stuff on the carryovers
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[FOLDER] tinycpu/ 28  4453d 13h earlz View Log RSS feed
[NODE][FOLDER] branches/ 1  4472d 15h root View Log RSS feed
[NODE][FOLDER] tags/ 1  4472d 15h root View Log RSS feed
[NODE][FOLDER] trunk/ 28  4453d 13h earlz View Log RSS feed
[NODE][NODE][FOLDER] docs/ 27  4453d 19h earlz View Log RSS feed
[NODE][NODE][FOLDER] simulation/ 2  4472d 13h earlz View Log RSS feed
[NODE][NODE][FOLDER] src/ 28  4453d 13h earlz View Log RSS feed
[NODE][NODE][NODE][FILE] alu.vhd 15  4465d 10h earlz View Log RSS feed
[NODE][NODE][NODE][FILE] blockram.vhd 11  4469d 11h earlz View Log RSS feed
[NODE][NODE][NODE][FILE] carryover.vhd 21  4455d 10h earlz View Log RSS feed
[NODE][NODE][NODE][FILE] core.vhd 28  4453d 13h earlz View Log RSS feed
[NODE][NODE][NODE][FILE] fetch.vhd 22  4455d 10h earlz View Log RSS feed
[NODE][NODE][NODE][FILE] memory.vhd 19  4456d 11h earlz View Log RSS feed
[NODE][NODE][NODE][FILE] registerfile.vhd 28  4453d 13h earlz View Log RSS feed
[NODE][NODE][NODE][FILE] tinycpu.vhd 13  4465d 21h earlz View Log RSS feed
[NODE][NODE][NODE][FILE] top.vhd 23  4454d 18h earlz View Log RSS feed
[NODE][NODE][FOLDER] testbench/ 28  4453d 13h earlz View Log RSS feed

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