URL
https://opencores.org/ocsvn/uart16550/uart16550/trunk
Subversion Repositories uart16550
[/] [uart16550/] [trunk/] [sim/] [rtl_sim/] [bin/] - Rev 50
Go to most recent revision | Changes | View Log | RSS feed
Last modification
- Rev 50 2001-12-06 14:51:10 GMT
- Author: gorban
- Log message:
- Bug in LSR[0] is fixed.
All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.