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Subversion Repositories uart2bus

[/] [uart2bus/] [trunk/] [doc/] - Rev 14

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Last modification

  • Rev 12 2012-02-25 10:48:40 GMT
  • Author: motilito
  • Log message:
    Updated Verilog implementation to sync with VHDL to include internal bus request/grant mechanism.
Path Last modification Log RSS feed
[FOLDER] uart2bus/ 14  2866d 00h motilito View Log RSS feed
[NODE][FOLDER] branches/ 1  5398d 09h root View Log RSS feed
[NODE][FOLDER] tags/ 1  5398d 09h root View Log RSS feed
[NODE][FOLDER] trunk/ 14  2866d 00h motilito View Log RSS feed
[NODE][NODE][FOLDER] doc/ 12  4655d 17h motilito View Log RSS feed
[NODE][NODE][NODE][FILE] UART to Bus Core Specifications.pdf 12  4655d 17h motilito View Log RSS feed
[NODE][NODE][FOLDER] scilab/ 7  4993d 07h motilito View Log RSS feed
[NODE][NODE][FOLDER] verilog/ 12  4655d 17h motilito View Log RSS feed
[NODE][NODE][FOLDER] vhdl/ 13  3199d 14h smuller View Log RSS feed

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