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Subversion Repositories uart2bus

[/] [uart2bus/] [trunk/] [verilog/] [bench/] - Rev 12

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Last modification

  • Rev 12 2012-02-25 10:48:40 GMT
  • Author: motilito
  • Log message:
    Updated Verilog implementation to sync with VHDL to include internal bus request/grant mechanism.
Path Last modification Log RSS feed
[FOLDER] uart2bus/ 12  4644d 20h motilito View Log RSS feed
[NODE][FOLDER] branches/ 1  5387d 12h root View Log RSS feed
[NODE][FOLDER] tags/ 1  5387d 12h root View Log RSS feed
[NODE][FOLDER] trunk/ 12  4644d 20h motilito View Log RSS feed
[NODE][NODE][FOLDER] doc/ 12  4644d 20h motilito View Log RSS feed
[NODE][NODE][FOLDER] scilab/ 7  4982d 10h motilito View Log RSS feed
[NODE][NODE][FOLDER] verilog/ 12  4644d 20h motilito View Log RSS feed
[NODE][NODE][NODE][FOLDER] bench/ 12  4644d 20h motilito View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] reg_file_model.v 2  5384d 18h motilito View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] tb_bin_uart2bus_top.v 12  4644d 20h motilito View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] tb_txt_uart2bus_top.v 12  4644d 20h motilito View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] tb_uart2bus_top.v 12  4644d 20h motilito View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] timescale.v 2  5384d 18h motilito View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] uart_tasks.v 12  4644d 20h motilito View Log RSS feed
[NODE][NODE][NODE][FOLDER] rtl/ 12  4644d 20h motilito View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 4  5338d 11h motilito View Log RSS feed
[NODE][NODE][NODE][FOLDER] syn/ 2  5384d 18h motilito View Log RSS feed
[NODE][NODE][FOLDER] vhdl/ 11  4646d 11h smuller View Log RSS feed

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