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Subversion Repositories uart_fifo_cpu_if_sv_testbench

[/] [uart_fifo_cpu_if_sv_testbench/] [trunk/] - Rev 2

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Last modification

  • Rev 2 2011-01-03 10:06:00 GMT
  • Author: andrewbridger
  • Log message:
    Added complete UART RTL and testbench. Both compile, but not debugged in simulator yet. Synchronous FIFO yet to be added. File headers need tidying.
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[FOLDER] uart_fifo_cpu_if_sv_testbench/ 2  4897d 22h andrewbridger View Log RSS feed
[NODE][FOLDER] branches/ 1  4897d 23h root View Log RSS feed
[NODE][FOLDER] tags/ 1  4897d 23h root View Log RSS feed
[NODE][FOLDER] trunk/ 2  4897d 22h andrewbridger View Log RSS feed
[NODE][NODE][FOLDER] bench/ 2  4897d 22h andrewbridger View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 2  4897d 22h andrewbridger View Log RSS feed
[NODE][NODE][FOLDER] sim/ 2  4897d 22h andrewbridger View Log RSS feed

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