OpenCores
URL https://opencores.org/ocsvn/uart_fifo_cpu_if_sv_testbench/uart_fifo_cpu_if_sv_testbench/trunk

Subversion Repositories uart_fifo_cpu_if_sv_testbench

[/] [uart_fifo_cpu_if_sv_testbench/] [trunk/] - Rev 3

Rev

Go to most recent revision | Changes | View Log | RSS feed

Last modification

  • Rev 3 2011-01-03 21:12:44 GMT
  • Author: andrewbridger
  • Log message:
    Changed to send and receive least significant bit first.
Path Last modification Log RSS feed
[FOLDER] uart_fifo_cpu_if_sv_testbench/ 3  4897d 09h andrewbridger View Log RSS feed
[NODE][FOLDER] branches/ 1  4897d 22h root View Log RSS feed
[NODE][FOLDER] tags/ 1  4897d 22h root View Log RSS feed
[NODE][FOLDER] trunk/ 3  4897d 09h andrewbridger View Log RSS feed
[NODE][NODE][FOLDER] bench/ 3  4897d 09h andrewbridger View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 3  4897d 09h andrewbridger View Log RSS feed
[NODE][NODE][FOLDER] sim/ 2  4897d 20h andrewbridger View Log RSS feed

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.