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Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [rtl/] - Rev 15

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Last modification

  • Rev 15 2010-02-04 14:21:43 GMT
  • Author: mikaeljf
  • Log message:
    Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.
Path Last modification Log RSS feed
[FOLDER] versatile_mem_ctrl/ 15  5407d 14h mikaeljf View Log RSS feed
[NODE][FOLDER] branches/ 1  5638d 16h root View Log RSS feed
[NODE][FOLDER] tags/ 1  5638d 16h root View Log RSS feed
[NODE][FOLDER] trunk/ 15  5407d 14h mikaeljf View Log RSS feed
[NODE][NODE][FOLDER] backend/ 8  5631d 12h unneback View Log RSS feed
[NODE][NODE][FOLDER] bench/ 15  5407d 14h mikaeljf View Log RSS feed
[NODE][NODE][FOLDER] doc/ 2  5638d 16h unneback View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 15  5407d 14h mikaeljf View Log RSS feed
[NODE][NODE][NODE][FOLDER] verilog/ 15  5407d 14h mikaeljf View Log RSS feed
[NODE][NODE][FOLDER] sim/ 15  5407d 14h mikaeljf View Log RSS feed
[NODE][NODE][FOLDER] syn/ 15  5407d 14h mikaeljf View Log RSS feed
[NODE][FOLDER] web_uploads/ 1  5638d 16h root View Log RSS feed

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