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Subversion Repositories versatile_mem_ctrl

[/] [versatile_mem_ctrl/] [trunk/] [syn/] [altera/] [run/] - Rev 113

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Last modification

  • Rev 15 2010-02-04 14:21:43 GMT
  • Author: mikaeljf
  • Log message:
    Added module 'dcm_pll.v' with Xilinx DCM and Altera altpll, also added module 'ddr_ff.v' with Xilinx IDDR/ODDR and Altera altddio_in/altddio_out. Added simple simulation script for Xilinx and Altera. Added simple synthesis script and SDC timing constraints for Altera.
Path Last modification Log RSS feed
[FOLDER] versatile_mem_ctrl/ 113  4696d 09h unneback View Log RSS feed
[NODE][FOLDER] branches/ 1  5480d 12h root View Log RSS feed
[NODE][FOLDER] tags/ 109  4696d 11h unneback View Log RSS feed
[NODE][FOLDER] trunk/ 113  4696d 09h unneback View Log RSS feed
[NODE][NODE][FOLDER] backend/ 8  5473d 08h unneback View Log RSS feed
[NODE][NODE][FOLDER] bench/ 106  4870d 03h unneback View Log RSS feed
[NODE][NODE][FOLDER] doc/ 108  4696d 11h unneback View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 113  4696d 09h unneback View Log RSS feed
[NODE][NODE][FOLDER] sim/ 86  5118d 17h mikaeljf View Log RSS feed
[NODE][NODE][FOLDER] syn/ 86  5118d 17h mikaeljf View Log RSS feed
[NODE][NODE][NODE][FOLDER] altera/ 86  5118d 17h mikaeljf View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] bin/ 86  5118d 17h mikaeljf View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] run/ 15  5249d 10h mikaeljf View Log RSS feed
[NODE][NODE][NODE][FOLDER] xilinx/ 19  5244d 13h mikaeljf View Log RSS feed
[NODE][FOLDER] web_uploads/ 1  5480d 12h root View Log RSS feed

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