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[/] [wbddr3/] [trunk/] [rtl/] - Rev 17

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  • Rev 17 2016-08-23 21:01:36 GMT
  • Author: dgisselq
  • Log message:
    Here are files from my current attempts to include the DDR3 SDRAM into an
    Arty project. Although a part of the Arty project, and not really sub modules
    to anything here, they really belong with this project.
Path Last modification Log RSS feed
[FOLDER] wbddr3/ 17  2847d 21h dgisselq View Log RSS feed
[NODE][FOLDER] branches/ 1  2874d 12h root View Log RSS feed
[NODE][FOLDER] tags/ 1  2874d 12h root View Log RSS feed
[NODE][FOLDER] trunk/ 17  2847d 21h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] bench/ 16  2851d 20h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] doc/ 15  2855d 02h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 17  2847d 21h dgisselq View Log RSS feed
[NODE][NODE][NODE][FILE] ddr3insert.v 17  2847d 21h dgisselq View Log RSS feed
[NODE][NODE][NODE][FILE] Makefile 2  2874d 08h dgisselq View Log RSS feed
[NODE][NODE][NODE][FILE] wbddrsdram.v 17  2847d 21h dgisselq View Log RSS feed
[NODE][NODE][NODE][FILE] xioddrserdes.v 17  2847d 21h dgisselq View Log RSS feed
[NODE][NODE][NODE][FILE] xoddrserdes.v 17  2847d 21h dgisselq View Log RSS feed

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