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[/] [xgate/] [trunk/] [bench/] [verilog/] - Rev 54

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Last modification

  • Rev 54 2010-01-27 17:33:58 GMT
  • Author: rehayes
  • Log message:
    complete rewrite of the bus arbitration module. Moved system test registers to new WISHBONE slave module.
Path Last modification Log RSS feed
[FOLDER] xgate/ 54  5586d 04h rehayes View Log RSS feed
[NODE][FOLDER] branches/ 1  5765d 03h root View Log RSS feed
[NODE][FOLDER] tags/ 1  5765d 03h root View Log RSS feed
[NODE][FOLDER] trunk/ 54  5586d 04h rehayes View Log RSS feed
[NODE][NODE][FOLDER] bench/ 54  5586d 04h rehayes View Log RSS feed
[NODE][NODE][NODE][FOLDER] verilog/ 54  5586d 04h rehayes View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] debug_test.v 54  5586d 04h rehayes View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] inst_test.v 50  5602d 01h rehayes View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] jump_mem.v 5  5725d 01h rehayes View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] ram.v 37  5665d 05h rehayes View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] simple_mem.v 2  5732d 23h rehayes View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] timescale.v 2  5732d 23h rehayes View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] tst_bench_top.v 54  5586d 04h rehayes View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] wb_master_model.v 35  5665d 05h rehayes View Log RSS feed
[NODE][NODE][NODE][FOLDER] xgate_test_code/ 39  5665d 04h rehayes View Log RSS feed
[NODE][NODE][FOLDER] doc/ 49  5602d 01h rehayes View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 53  5586d 04h rehayes View Log RSS feed
[NODE][NODE][FOLDER] sim/ 32  5665d 06h rehayes View Log RSS feed
[NODE][NODE][FOLDER] sw/ 52  5586d 04h rehayes View Log RSS feed

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