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[/] [xgate/] [trunk/] [rtl/] [verilog/] - Rev 12

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Last modification

  • Rev 12 2009-09-23 20:50:59 GMT
  • Author: rehayes
  • Log message:
    Single step debug working, added software error interrupt output, added WISHBONE master module, fixed control register bits
Path Last modification Log RSS feed
[FOLDER] xgate/ 12  5540d 08h rehayes View Log RSS feed
[NODE][FOLDER] branches/ 1  5593d 11h root View Log RSS feed
[NODE][FOLDER] tags/ 1  5593d 11h root View Log RSS feed
[NODE][FOLDER] trunk/ 12  5540d 08h rehayes View Log RSS feed
[NODE][NODE][FOLDER] bench/ 11  5540d 08h rehayes View Log RSS feed
[NODE][NODE][FOLDER] doc/ 5  5553d 08h rehayes View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 12  5540d 08h rehayes View Log RSS feed
[NODE][NODE][NODE][FOLDER] verilog/ 12  5540d 08h rehayes View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] xgate_irq_encode.v 2  5561d 06h rehayes View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] xgate_regs.v 12  5540d 08h rehayes View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] xgate_risc.v 12  5540d 08h rehayes View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] xgate_top.v 12  5540d 08h rehayes View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] xgate_wbm_bus.v 12  5540d 08h rehayes View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] xgate_wbs_bus.v 5  5553d 08h rehayes View Log RSS feed
[NODE][NODE][FOLDER] sim/ 5  5553d 08h rehayes View Log RSS feed

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