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[/] [xgate/] [trunk/] [rtl/] [verilog/] - Rev 5

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Last modification

  • Rev 5 2009-09-10 20:41:02 GMT
  • Author: rehayes
  • Log message:
    Update for memory wait states, testbench and instruction decoder simplified for synthesis
Path Last modification Log RSS feed
[FOLDER] xgate/ 5  5553d 09h rehayes View Log RSS feed
[NODE][FOLDER] branches/ 1  5593d 11h root View Log RSS feed
[NODE][FOLDER] tags/ 1  5593d 11h root View Log RSS feed
[NODE][FOLDER] trunk/ 5  5553d 09h rehayes View Log RSS feed
[NODE][NODE][FOLDER] bench/ 5  5553d 09h rehayes View Log RSS feed
[NODE][NODE][FOLDER] doc/ 5  5553d 09h rehayes View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 5  5553d 09h rehayes View Log RSS feed
[NODE][NODE][NODE][FOLDER] verilog/ 5  5553d 09h rehayes View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] xgate_irq_encode.v 2  5561d 06h rehayes View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] xgate_regs.v 2  5561d 06h rehayes View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] xgate_risc.v 5  5553d 09h rehayes View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] xgate_top.v 5  5553d 09h rehayes View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] xgate_wbs_bus.v 5  5553d 09h rehayes View Log RSS feed
[NODE][NODE][FOLDER] sim/ 5  5553d 09h rehayes View Log RSS feed

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