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[/] [xgate/] [trunk/] [rtl/] [verilog/] - Rev 53
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Last modification
- Rev 53 2010-01-27 17:29:16 GMT
- Author: rehayes
- Log message:
- Extensive changes to fix errors in how wait state are handled by the master bus interface and the RISC control logic. Fix to slave mode WISHBONE ack signal.