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[/] [xulalx25soc/] [trunk/] - Rev 61

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Last modification

  • Rev 61 2016-06-09 00:51:19 GMT
  • Author: dgisselq
  • Log message:
    Fixed the timing control wires: busy and valid will never both be true. Busy
    will be true (now) until valid is asserted, and busy will never not be
    asserted until valid is true.
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[NODE][NODE][FOLDER] bench/ 47  3148d 16h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] doc/ 31  3160d 15h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 61  3070d 13h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] sw/ 53  3118d 13h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] xilinx/ 22  3172d 18h dgisselq View Log RSS feed
[NODE][NODE][FILE] Makefile 39  3155d 18h dgisselq View Log RSS feed
[NODE][NODE][FILE] xula.ucf 6  3231d 10h dgisselq View Log RSS feed

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