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[/] [xulalx25soc/] [trunk/] [doc/] - Rev 31

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  • Rev 31 2016-03-10 23:01:08 GMT
  • Author: dgisselq
  • Log message:
    A bug fix, although one that rearranges the bus. The first four I/O locations
    have been adjusted. The new locations are reflected in wishbone.html. In
    addition, the PWM and UART devices no longer create bus errors when accessed.
    Finally, this version uses a `define XULA25 to determine whether or not to build
    for the XuLA2-LX9 or the XuLA2-LX25. If defined, it will build for the
    XuLA2-LX25. If not, for the XuLA2-LX9. The ideal location for this define
    would be to place it into your Xilinx configuration, should you wish to build
    for the LX25.
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[FOLDER] xulalx25soc/ 31  3184d 17h dgisselq View Log RSS feed
[NODE][FOLDER] branches/ 1  3255d 14h root View Log RSS feed
[NODE][FOLDER] tags/ 1  3255d 14h root View Log RSS feed
[NODE][FOLDER] trunk/ 31  3184d 17h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] bench/ 31  3184d 17h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] doc/ 31  3184d 17h dgisselq View Log RSS feed
[NODE][NODE][NODE][FILE] icapspec.pdf 20  3247d 03h dgisselq View Log RSS feed
[NODE][NODE][NODE][FILE] qspispec.pdf 20  3247d 03h dgisselq View Log RSS feed
[NODE][NODE][NODE][FILE] rtcspec.pdf 20  3247d 03h dgisselq View Log RSS feed
[NODE][NODE][NODE][FILE] scopspec.pdf 20  3247d 03h dgisselq View Log RSS feed
[NODE][NODE][NODE][DB-FILE] wishbone.html 31  3184d 17h dgisselq View Log RSS feed
[NODE][NODE][NODE][FILE] zipspec.pdf 20  3247d 03h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 31  3184d 17h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] sw/ 31  3184d 17h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] xilinx/ 22  3196d 20h dgisselq View Log RSS feed

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