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[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [src/] [top/] - Rev 21
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Last modification
- Rev 21 2021-06-13 06:33:52 GMT
- Author: dinesha
- Log message:
- Simulation clean up and wishbone interconnect added