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[/] [zipcpu/] [trunk/] [rtl/] - Rev 118

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  • Rev 118 2016-04-02 23:29:56 GMT
  • Author: dgisselq
  • Log message:
    Fixes two bugs: 1) in the early branching code within the instruction decoder.
    This prevented the early branching from working when built with Xilinx's tools,
    while the code worked with Verilator. 2) The CPU was not working with the
    traditional cache and early branching disabled. These two bugs masked each
    other. The replacement code is simpler.
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[FOLDER] zipcpu/ 118  3139d 07h dgisselq View Log RSS feed
[NODE][FOLDER] branches/ 1  3390d 14h root View Log RSS feed
[NODE][FOLDER] tags/ 1  3390d 14h root View Log RSS feed
[NODE][FOLDER] trunk/ 118  3139d 07h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] bench/ 105  3163d 15h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] doc/ 107  3158d 08h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 118  3139d 07h dgisselq View Log RSS feed
[NODE][NODE][NODE][FOLDER] aux/ 69  3241d 14h dgisselq View Log RSS feed
[NODE][NODE][NODE][FOLDER] core/ 118  3139d 07h dgisselq View Log RSS feed
[NODE][NODE][NODE][FOLDER] peripherals/ 88  3228d 08h dgisselq View Log RSS feed
[NODE][NODE][NODE][FILE] cpudefs.v 84  3230d 07h dgisselq View Log RSS feed
[NODE][NODE][NODE][FILE] Makefile 105  3163d 15h dgisselq View Log RSS feed
[NODE][NODE][NODE][FILE] zipbones.v 105  3163d 15h dgisselq View Log RSS feed
[NODE][NODE][NODE][FILE] zipsystem.v 115  3139d 15h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] sw/ 117  3139d 15h dgisselq View Log RSS feed

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