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https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
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[/] [zipcpu/] [trunk/] [rtl/] - Rev 38
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Last modification
- Rev 38 2015-09-29 16:38:09 GMT
- Author: dgisselq
- Log message:
- A couple of quick updates:
- The Zip CPU now supports pipelined memory access at one clock per
instruction (assuming all the instructions are in the cache)
- There is now a 'zipbones' module to build a Zip System without peripherals.
Any peripherals would then need to be external to the CPU.
- Some bug fixes.
Documentation changes coming shortly.