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[/] [light8080/] [trunk/] [sw/] [demos/] - Rev 78

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Last modification

  • Rev 78 2012-04-10 19:42:40 GMT
  • Author: ja_rd
  • Log message:
    Fixed a number of errors in the last refactor of the VHDL side of the project:
    - Path errors in the simulation scripts.
    - The reset pin in the C2SB mini-test-bench was not being driven.
    - The main vhdl test bench file was missing entirely.

    All of these errors due to not properly verifying the commit...
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[FOLDER] light8080/ 78  4420d 01h ja_rd View Log RSS feed
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[NODE][FOLDER] trunk/ 78  4420d 01h ja_rd View Log RSS feed
[NODE][NODE][FOLDER] c/ 68  4442d 03h motilito View Log RSS feed
[NODE][NODE][FOLDER] doc/ 76  4427d 15h motilito View Log RSS feed
[NODE][NODE][FOLDER] sim/ 78  4420d 01h ja_rd View Log RSS feed
[NODE][NODE][FOLDER] sw/ 78  4420d 01h ja_rd View Log RSS feed
[NODE][NODE][NODE][FOLDER] demos/ 78  4420d 01h ja_rd View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] c2sb/ 78  4420d 01h ja_rd View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] hello/ 77  4420d 23h ja_rd View Log RSS feed
[NODE][NODE][NODE][FOLDER] tb/ 74  4431d 07h ja_rd View Log RSS feed
[NODE][NODE][FOLDER] synthesis/ 46  5416d 17h ja_rd View Log RSS feed
[NODE][NODE][FOLDER] tools/ 73  4431d 07h ja_rd View Log RSS feed
[NODE][NODE][FOLDER] ucode/ 64  4478d 11h ja_rd View Log RSS feed
[NODE][NODE][FOLDER] util/ 64  4478d 11h ja_rd View Log RSS feed
[NODE][NODE][FOLDER] verilog/ 68  4442d 03h motilito View Log RSS feed
[NODE][NODE][FOLDER] vhdl/ 78  4420d 01h ja_rd View Log RSS feed
[NODE][FOLDER] web_uploads/ 33  5547d 07h root View Log RSS feed

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