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[/] [light8080/] [trunk/] [verilog/] [bench/] - Rev 90

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  • Rev 66 2012-03-03 17:58:06 GMT
  • Author: motilito
  • Log message:
    Adding interrupt example code to the Verilog implementation. An interrupt controller was added to the sample SOC module and a sample code was added to the "hello.c" example code.
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[FOLDER] light8080/ 90  3301d 06h motilito View Log RSS feed
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[NODE][FOLDER] trunk/ 90  3301d 06h motilito View Log RSS feed
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[NODE][NODE][FOLDER] sw/ 87  4390d 01h ja_rd View Log RSS feed
[NODE][NODE][FOLDER] synthesis/ 46  5392d 19h ja_rd View Log RSS feed
[NODE][NODE][FOLDER] tools/ 90  3301d 06h motilito View Log RSS feed
[NODE][NODE][FOLDER] ucode/ 64  4454d 13h ja_rd View Log RSS feed
[NODE][NODE][FOLDER] util/ 64  4454d 13h ja_rd View Log RSS feed
[NODE][NODE][FOLDER] verilog/ 90  3301d 06h motilito View Log RSS feed
[NODE][NODE][NODE][FOLDER] bench/ 66  4434d 05h motilito View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] tb_l80soc.v 66  4434d 05h motilito View Log RSS feed
[NODE][NODE][NODE][FOLDER] rtl/ 88  4377d 09h motilito View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 66  4434d 05h motilito View Log RSS feed
[NODE][NODE][NODE][FOLDER] syn/ 90  3301d 06h motilito View Log RSS feed
[NODE][NODE][FOLDER] vhdl/ 85  4390d 02h ja_rd View Log RSS feed
[NODE][FOLDER] web_uploads/ 33  5523d 09h root View Log RSS feed

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