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[/] [light8080/] [trunk/] [verilog/] [sim/] - Rev 90

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  • Rev 66 2012-03-03 17:58:06 GMT
  • Author: motilito
  • Log message:
    Adding interrupt example code to the Verilog implementation. An interrupt controller was added to the sample SOC module and a sample code was added to the "hello.c" example code.
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[NODE][NODE][NODE][FOLDER] rtl/ 88  4372d 10h motilito View Log RSS feed
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