URL https://opencores.org/ocsvn/minimips_superscalar/minimips_superscalar/trunk

Last modification

• Rev 18 2019-03-23 04:25:17 GMT
• Author: mcafruni

• Log message:

  clock_gate.vhd: removed.
  minimips.vhd: Clock2 input is wrongly connected to the clock signal (Do not ask me how that happened. I'm sorry.). The right thing is to be connected to the clock2 signal. Adjusted.

Path	Last modification			Log	RSS feed
minimips_superscalar/	40	1415d 23h	mcafruni	View Log	RSS feed
branches/	1	1978d 04h	root	View Log	RSS feed
tags/	37	1510d 00h	mcafruni	View Log	RSS feed
trunk/	40	1415d 23h	mcafruni	View Log	RSS feed
bench/	25	1512d 20h	mcafruni	View Log	RSS feed
benchmarks/	40	1415d 23h	mcafruni	View Log	RSS feed
gasm_with_mult2_instruction/	6	1977d 09h	mcafruni	View Log	RSS feed
sources/	18	1886d 19h	mcafruni	View Log	RSS feed
alu.vhd	2	1977d 18h	mcafruni	View Log	RSS feed
alu2.vhd	2	1977d 18h	mcafruni	View Log	RSS feed
banc.vhd	2	1977d 18h	mcafruni	View Log	RSS feed
bus_ctrl01.vhd	2	1977d 18h	mcafruni	View Log	RSS feed
bus_ctrl02.vhd	2	1977d 18h	mcafruni	View Log	RSS feed
delay_gate.vhd	2	1977d 18h	mcafruni	View Log	RSS feed
minimips.vhd	18	1886d 19h	mcafruni	View Log	RSS feed
pack_mips.vhd	2	1977d 18h	mcafruni	View Log	RSS feed
pps_di.vhd	2	1977d 18h	mcafruni	View Log	RSS feed
pps_di_2.vhd	2	1977d 18h	mcafruni	View Log	RSS feed
pps_ei.vhd	2	1977d 18h	mcafruni	View Log	RSS feed
pps_ei_2.vhd	2	1977d 18h	mcafruni	View Log	RSS feed
pps_ex.vhd	2	1977d 18h	mcafruni	View Log	RSS feed
pps_ex_2.vhd	2	1977d 18h	mcafruni	View Log	RSS feed
pps_mem.vhd	2	1977d 18h	mcafruni	View Log	RSS feed
pps_pf.vhd	7	1964d 20h	mcafruni	View Log	RSS feed
renvoi.vhd	2	1977d 18h	mcafruni	View Log	RSS feed
syscop.vhd	2	1977d 18h	mcafruni	View Log	RSS feed