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[/] [minsoc/] [branches/] [rc-1.0/] - Rev 124

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Last modification

  • Rev 124 2011-11-02 15:27:24 GMT
  • Author: rfajardo
  • Log message:
    Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever.
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[NODE][NODE][NODE][FOLDER] backend/ 124  3244d 22h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] bench/ 124  3244d 22h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] doc/ 101  3287d 06h rfajardo View Log RSS feed
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[NODE][NODE][NODE][FOLDER] rtl/ 110  3251d 16h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 121  3250d 18h rfajardo View Log RSS feed
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[NODE][NODE][NODE][FOLDER] syn/ 121  3250d 18h rfajardo View Log RSS feed
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