OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [rc-1.0/] [backend/] [ug257/] - Rev 147

Rev

Go to most recent revision | Changes | View Log | RSS feed

Last modification

  • Rev 147 2011-11-23 12:29:02 GMT
  • Author: rfajardo
  • Log message:
    Updating minsoc_bench.v to correctly acquire uart data.

    Uart drivers: when an end of line character was sent, the driver appended a carriage return to it. This is not necessary and has been removed.
    -Eth and Uart firmwares also had a carriage return after the end of line, also removed.

    Minsoc_bench_defines.v: Renaming VCD_OUTPUT define to WAVEFORM_OUTPUT

    run_bench: selecting -lxt2 for waveform output format. This output format size is 10 times smaller than vcd.

    minsoc-install.sh: lxt2 output format requires that Icarus Verilog be installed with zlib support. For that, we now check if zlib is supported on script run.
Path Last modification Log RSS feed
[FOLDER] minsoc/ 147  3292d 00h rfajardo View Log RSS feed
[NODE][FOLDER] branches/ 147  3292d 00h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rc-1.0/ 147  3292d 00h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] backend/ 147  3292d 00h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] altera_3c25_board/ 147  3292d 00h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] spartan3a_dsp_kit/ 147  3292d 00h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] spartan3e_starter_kit/ 147  3292d 00h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] std/ 147  3292d 00h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] ug257/ 147  3292d 00h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][H-FILE] board.h 146  3292d 06h ConX. View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] configure 146  3292d 06h ConX. View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] gcc-opt.mk 146  3292d 06h ConX. View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] minsoc_bench_defines.v 147  3292d 00h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] minsoc_defines.v 146  3292d 06h ConX. View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] or1200_defines.v 146  3292d 06h ConX. View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] orp.ld 146  3292d 06h ConX. View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] ug257.ucf 146  3292d 06h ConX. View Log RSS feed
[NODE][NODE][NODE][FOLDER] bench/ 147  3292d 00h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] doc/ 101  3355d 05h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] prj/ 133  3308d 03h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] rtl/ 110  3319d 15h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 147  3292d 00h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sw/ 147  3292d 00h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] syn/ 121  3318d 17h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] utils/ 147  3292d 00h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] verilator/ 140  3293d 02h rfajardo View Log RSS feed
[NODE][FOLDER] tags/ 42  3544d 22h rfajardo View Log RSS feed
[NODE][FOLDER] trunk/ 144  3293d 01h rfajardo View Log RSS feed

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.