OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [rc-1.0/] [bench/] - Rev 124

Rev

Go to most recent revision | Changes | View Log | RSS feed

Last modification

  • Rev 124 2011-11-02 15:27:24 GMT
  • Author: rfajardo
  • Log message:
    Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever.
Path Last modification Log RSS feed
[FOLDER] minsoc/ 124  4544d 20h rfajardo View Log RSS feed
[NODE][FOLDER] branches/ 124  4544d 20h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rc-1.0/ 124  4544d 20h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] backend/ 124  4544d 20h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] bench/ 124  4544d 20h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] verilog/ 124  4544d 20h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] doc/ 101  4587d 04h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] prj/ 120  4550d 19h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] rtl/ 110  4551d 14h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 121  4550d 16h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sw/ 80  4620d 01h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] syn/ 121  4550d 16h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] utils/ 122  4550d 14h rfajardo View Log RSS feed
[NODE][FOLDER] tags/ 42  4776d 21h rfajardo View Log RSS feed
[NODE][FOLDER] trunk/ 108  4551d 19h rfajardo View Log RSS feed

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.