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[/] [minsoc/] [branches/] [rc-1.0/] [bench/] - Rev 124

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Last modification

  • Rev 124 2011-11-02 15:27:24 GMT
  • Author: rfajardo
  • Log message:
    Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever.
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[FOLDER] minsoc/ 124  3309d 15h rfajardo View Log RSS feed
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[NODE][NODE][FOLDER] rc-1.0/ 124  3309d 15h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] backend/ 124  3309d 15h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] bench/ 124  3309d 15h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] verilog/ 124  3309d 15h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] doc/ 101  3351d 23h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] prj/ 120  3315d 14h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] rtl/ 110  3316d 09h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 121  3315d 11h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sw/ 80  3384d 20h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] syn/ 121  3315d 11h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] utils/ 122  3315d 10h rfajardo View Log RSS feed
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[NODE][FOLDER] trunk/ 108  3316d 14h rfajardo View Log RSS feed

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