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[/] [minsoc/] [branches/] [rc-1.0/] [bench/] [verilog/] - Rev 124

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Last modification

  • Rev 124 2011-11-02 15:27:24 GMT
  • Author: rfajardo
  • Log message:
    Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever.
Path Last modification Log RSS feed
[FOLDER] minsoc/ 124  4042d 09h rfajardo View Log RSS feed
[NODE][FOLDER] branches/ 124  4042d 09h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rc-1.0/ 124  4042d 09h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] backend/ 124  4042d 09h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] bench/ 124  4042d 09h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] verilog/ 124  4042d 09h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FOLDER] sim_lib/ 27  4603d 10h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FOLDER] vpi/ 71  4218d 14h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] minsoc_bench.v 124  4042d 09h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] minsoc_memory_model.v 71  4218d 14h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] doc/ 101  4084d 17h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] prj/ 120  4048d 08h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] rtl/ 110  4049d 03h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 121  4048d 05h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sw/ 80  4117d 13h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] syn/ 121  4048d 05h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] utils/ 122  4048d 03h rfajardo View Log RSS feed
[NODE][FOLDER] tags/ 42  4274d 10h rfajardo View Log RSS feed
[NODE][FOLDER] trunk/ 108  4049d 08h rfajardo View Log RSS feed

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