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[/] [minsoc/] [branches/] [rc-1.0/] [bench/] [verilog/] - Rev 124

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Last modification

  • Rev 124 2011-11-02 15:27:24 GMT
  • Author: rfajardo
  • Log message:
    Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever.
Path Last modification Log RSS feed
[FOLDER] minsoc/ 124  3319d 18h rfajardo View Log RSS feed
[NODE][FOLDER] branches/ 124  3319d 18h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rc-1.0/ 124  3319d 18h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] backend/ 124  3319d 18h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] bench/ 124  3319d 18h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] verilog/ 124  3319d 18h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FOLDER] sim_lib/ 27  3880d 20h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FOLDER] vpi/ 71  3495d 23h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] minsoc_bench.v 124  3319d 18h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] minsoc_memory_model.v 71  3495d 23h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] doc/ 101  3362d 02h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] prj/ 120  3325d 17h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] rtl/ 110  3326d 12h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 121  3325d 14h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sw/ 80  3394d 23h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] syn/ 121  3325d 14h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] utils/ 122  3325d 13h rfajardo View Log RSS feed
[NODE][FOLDER] tags/ 42  3551d 19h rfajardo View Log RSS feed
[NODE][FOLDER] trunk/ 108  3326d 17h rfajardo View Log RSS feed

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