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[/] [minsoc/] [branches/] [rc-1.0/] [bench/] [verilog/] - Rev 129

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Last modification

  • Rev 129 2011-11-03 00:31:18 GMT
  • Author: rfajardo
  • Log message:
    Removing bugs introduced when splitting clocks and reset.
    1) NEGATIVE_RESET or POSITIVE_RESET were missing as definition on minsoc_bench_clock.v (include minsoc_defines.v).
    2) wait for reset on minsoc_bench.v to assert design_ready
Path Last modification Log RSS feed
[FOLDER] minsoc/ 129  4046d 16h rfajardo View Log RSS feed
[NODE][FOLDER] branches/ 129  4046d 16h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rc-1.0/ 129  4046d 16h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] backend/ 124  4047d 01h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] bench/ 129  4046d 16h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] verilog/ 129  4046d 16h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FOLDER] sim_lib/ 27  4608d 03h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FOLDER] vpi/ 71  4223d 06h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] minsoc_bench.v 129  4046d 16h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] minsoc_bench_clock.v 129  4046d 16h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] minsoc_memory_model.v 71  4223d 06h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] doc/ 101  4089d 09h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] prj/ 128  4046d 17h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] rtl/ 110  4053d 19h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 121  4052d 21h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sw/ 80  4122d 06h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] syn/ 121  4052d 21h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] utils/ 122  4052d 20h rfajardo View Log RSS feed
[NODE][FOLDER] tags/ 42  4279d 02h rfajardo View Log RSS feed
[NODE][FOLDER] trunk/ 108  4054d 00h rfajardo View Log RSS feed

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