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[/] [minsoc/] [branches/] [rc-1.0/] [bench/] [verilog/] - Rev 131

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Last modification

  • Rev 131 2011-11-03 13:58:53 GMT
  • Author: rfajardo
  • Log message:
    Renaming testbench modules. Adding to ifdefs without which the testbench generation can fail.
Path Last modification Log RSS feed
[FOLDER] minsoc/ 131  4548d 13h rfajardo View Log RSS feed
[NODE][FOLDER] branches/ 131  4548d 13h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rc-1.0/ 131  4548d 13h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] backend/ 124  4549d 11h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] bench/ 131  4548d 13h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] verilog/ 131  4548d 13h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FOLDER] sim_lib/ 27  5110d 12h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FOLDER] vpi/ 71  4725d 16h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] minsoc_bench_clock.v 131  4548d 13h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] minsoc_bench_core.v 131  4548d 13h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] minsoc_memory_model.v 71  4725d 16h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] doc/ 101  4591d 19h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] prj/ 131  4548d 13h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] rtl/ 110  4556d 05h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 121  4555d 07h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sw/ 80  4624d 15h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] syn/ 121  4555d 07h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] utils/ 122  4555d 05h rfajardo View Log RSS feed
[NODE][FOLDER] tags/ 42  4781d 12h rfajardo View Log RSS feed
[NODE][FOLDER] trunk/ 108  4556d 10h rfajardo View Log RSS feed

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