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[/] [minsoc/] [branches/] [rc-1.0/] [bench/] [verilog/] - Rev 133

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Last modification

  • Rev 133 2011-11-07 09:48:11 GMT
  • Author: rfajardo
  • Log message:
    Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock again.

    Applying Rubén Diez patch to avoid warnings on firmware load for simulation.
Path Last modification Log RSS feed
[FOLDER] minsoc/ 133  3276d 22h rfajardo View Log RSS feed
[NODE][FOLDER] branches/ 133  3276d 22h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rc-1.0/ 133  3276d 22h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] backend/ 124  3281d 17h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] bench/ 133  3276d 22h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] verilog/ 133  3276d 22h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FOLDER] sim_lib/ 27  3842d 18h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FOLDER] vpi/ 71  3457d 22h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] minsoc_bench.v 133  3276d 22h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] minsoc_bench_clock.v 131  3280d 18h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] minsoc_bench_core.v 133  3276d 22h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] minsoc_memory_model.v 71  3457d 22h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] doc/ 101  3324d 01h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] prj/ 133  3276d 22h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] rtl/ 110  3288d 10h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 133  3276d 22h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sw/ 133  3276d 22h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] syn/ 121  3287d 12h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] utils/ 122  3287d 11h rfajardo View Log RSS feed
[NODE][FOLDER] tags/ 42  3513d 18h rfajardo View Log RSS feed
[NODE][FOLDER] trunk/ 108  3288d 15h rfajardo View Log RSS feed

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