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[/] [minsoc/] [branches/] [rc-1.0/] [bench/] [verilog/] - Rev 145

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Last modification

  • Rev 145 2011-11-22 21:30:01 GMT
  • Author: rfajardo
  • Log message:
    minsoc_bench_core.v and minsoc_bench_clock.v left only on verilator branche. It will develop there until it is ported for inclusion into trunk. RC-1.0 is now clean of it.
Path Last modification Log RSS feed
[FOLDER] minsoc/ 145  3265d 06h rfajardo View Log RSS feed
[NODE][FOLDER] branches/ 145  3265d 06h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rc-1.0/ 145  3265d 06h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] backend/ 143  3265d 17h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] bench/ 145  3265d 06h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] verilog/ 145  3265d 06h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FOLDER] sim_lib/ 27  3846d 14h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FOLDER] vpi/ 71  3461d 17h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] minsoc_bench.v 133  3280d 18h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] minsoc_memory_model.v 71  3461d 17h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] doc/ 101  3327d 21h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] prj/ 133  3280d 18h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] rtl/ 110  3292d 06h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 134  3280d 17h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sw/ 133  3280d 18h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] syn/ 121  3291d 08h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] utils/ 143  3265d 17h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] verilator/ 140  3265d 18h rfajardo View Log RSS feed
[NODE][FOLDER] tags/ 42  3517d 14h rfajardo View Log RSS feed
[NODE][FOLDER] trunk/ 144  3265d 17h rfajardo View Log RSS feed

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