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[/] [minsoc/] [branches/] [rc-1.0/] [bench/] [verilog/] - Rev 71


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  • Rev 71 2011-05-10 10:34:10 GMT
  • Author: rfajardo
  • Log message:
    Modelsim whines about missing timescales:
    -minsoc_bench.v, minsoc_memory_model.v and dbg_comm_vpi.v updated to include timescale.v

    modelsim simulation working under Windows. Modelsim PE Student Edition 10.0a

    Simulation<->adv_jtag_bridge<->gdb communication not working perfectly. I believe VPI module has to be recompiled, used pre-compiled one for now.
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