OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [rc-1.0/] [prj/] [src/] - Rev 131

Rev

Go to most recent revision | Changes | View Log | RSS feed

Last modification

  • Rev 131 2011-11-03 13:58:53 GMT
  • Author: rfajardo
  • Log message:
    Renaming testbench modules. Adding to ifdefs without which the testbench generation can fail.
Path Last modification Log RSS feed
[FOLDER] minsoc/ 131  4043d 14h rfajardo View Log RSS feed
[NODE][FOLDER] branches/ 131  4043d 14h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rc-1.0/ 131  4043d 14h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] backend/ 124  4044d 12h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] bench/ 131  4043d 14h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] doc/ 101  4086d 20h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] prj/ 131  4043d 14h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] altera/ 97  4095d 19h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] scripts/ 110  4051d 06h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] sim/ 97  4095d 19h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] src/ 131  4043d 14h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FOLDER] blackboxes/ 113  4050d 14h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] adbg_top.prj 85  4101d 12h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] altera_virtual_jtag.prj 96  4096d 06h javieralso View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] ethmac.prj 120  4050d 11h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] jtag_top.prj 85  4101d 12h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] minsoc_bench.prj 131  4043d 14h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] minsoc_top.prj 89  4101d 11h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] or1200_top.prj 110  4051d 06h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] uart_top.prj 85  4101d 12h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] xilinx/ 97  4095d 19h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] rtl/ 110  4051d 06h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 121  4050d 08h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sw/ 80  4119d 17h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] syn/ 121  4050d 08h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] utils/ 122  4050d 07h rfajardo View Log RSS feed
[NODE][FOLDER] tags/ 42  4276d 13h rfajardo View Log RSS feed
[NODE][FOLDER] trunk/ 108  4051d 11h rfajardo View Log RSS feed

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.