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[/] [minsoc/] [branches/] [rc-1.0/] [rtl/] [verilog/] - Rev 175

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  • Rev 110 2011-10-26 21:41:05 GMT
  • Author: rfajardo
  • Log message:
    Fixing several minor issues with the system:
    -minsoc-install splitted into installation and configuration
    -minsoc-configure.sh can be used to configure a fresh checked out system
    -configure script used by both minsoc-configure.sh and minsoc-install.sh to configure

    -rtl/verilog: svn externals fixed
    -or1200 rolled back to release-1.0

    -prj/scripts:
    -Makefile has been used by simulation to differentiate project definition of vhdl and verilog files
    -Altera was differentiating it in script
    -now there are two scripts, one for vhdl and another for verilog. The differentiation occurs in Makefile as for simulation.
    -altera_3c25_board/configure scripts had to be updated, vprj and vhdprj file extensions used to differentiate Verilog and VHDL project files.

    -prj/src: or1200_top.prj downdated to definition of or1200_v1
Path Last modification Log RSS feed
[FOLDER] minsoc/ 175  4050d 01h rfajardo View Log RSS feed
[NODE][FOLDER] branches/ 153  4581d 09h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rc-1.0/ 152  4581d 09h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] backend/ 147  4586d 08h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] bench/ 148  4586d 06h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] doc/ 101  4649d 13h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] prj/ 133  4602d 10h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] rtl/ 110  4613d 23h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] verilog/ 110  4613d 23h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FOLDER] minsoc_startup/ 12  5340d 01h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] altera_pll.v 63  4794d 03h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] minsoc_clock_manager.v 62  4794d 10h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] minsoc_onchip_ram.v 7  5368d 04h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] minsoc_onchip_ram_top.v 7  5368d 04h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] minsoc_tc_top.v 7  5368d 04h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] minsoc_top.v 75  4690d 03h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] minsoc_xilinx_internal_jtag.v 2  5382d 08h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] timescale.v 70  4783d 10h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] xilinx_dcm.v 88  4664d 03h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 147  4586d 08h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sw/ 147  4586d 08h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] syn/ 121  4613d 01h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] utils/ 152  4581d 09h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] verilator/ 153  4581d 09h rfajardo View Log RSS feed
[NODE][FOLDER] tags/ 172  4134d 02h rfajardo View Log RSS feed
[NODE][FOLDER] trunk/ 175  4050d 01h rfajardo View Log RSS feed

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