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[/] [minsoc/] [branches/] [verilator/] [rtl/] [verilog/] - Rev 62

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Last modification

  • Rev 62 2011-04-29 10:32:37 GMT
  • Author: rfajardo
  • Log message:
    Wrapping different family modules of same manufacturer in a single module.

    minsoc_clock_manager.v: uses fpga manufacturer wrappers

    xilinx_dcm.v: selects between different Xilinx FPGA families and implements the module

    altera_pll.v: selects between different Altera FPGA families and implements the module
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[FOLDER] minsoc/ 62  4707d 17h rfajardo View Log RSS feed
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[NODE][FOLDER] tags/ 42  4752d 13h rfajardo View Log RSS feed
[NODE][FOLDER] trunk/ 62  4707d 17h rfajardo View Log RSS feed

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