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[/] [minsoc/] [branches/] [verilator/] [rtl/] [verilog/] - Rev 63


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Last modification

  • Rev 63 2011-04-29 17:26:11 GMT
  • Author: rfajardo
  • Log message:
    Adding a functional synthesis Makefile system. Still needs a reviews and enhancements, but at least it is something.
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