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[/] [minsoc/] [tags/] [release-0.9/] [bench/] [verilog/] [vpi/] - Rev 2
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Last modification
- Rev 2 2009-09-18 11:46:11 GMT
- Author: rfajardo
- Log message:
- First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit