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[/] [minsoc/] [tags/] [release-1.0/] - Rev 70

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  • Rev 70 2011-05-10 10:06:07 GMT
  • Author: rfajardo
  • Log message:
    Including a global timescale under minsoc/rtl/verilog to control simulation. It is under the implementation because the implementation files include it.

    Removing timescale definition of minsoc_bench_defines.v files.

    Creating a modelsim simulation directory. Everything is working under Linux. For Windows, run_sim.sh has to be changed:
    -pli ../../bench/verilog/vpi/jp-io-vpi.so
    to:
    -pli ../../bench/verilog/vpi/jp-io-vpi.dll

    These files have to be compiled/copied from minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_platform to minsoc/bench/verilog/vpi.
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[FOLDER] minsoc/ 70  4933d 06h rfajardo View Log RSS feed
[NODE][FOLDER] branches/ 1  5532d 06h root View Log RSS feed
[NODE][FOLDER] tags/ 42  4989d 01h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] release-0.9/ 42  4989d 01h rfajardo View Log RSS feed
[NODE][FOLDER] trunk/ 70  4933d 06h rfajardo View Log RSS feed

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